Digital Electronics-Combinational Logic Circuits, Minimization of Boolean Functions [GATE (Graduate Aptitude Test in Engineering) Instrumentation]: Questions 1 - 7 of 12

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Question 1

Question MCQ▾

How many entries will be in the truth table of 4 input NAND gate?

Choices

Choice (4)Response

a.

16

b.

64

c.

32

d.

8

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Question 2

Question MCQ▾

The Boolean theorem corresponds to

Choices

Choice (4)Response

a.

b.

c.

d.

Edit

Question 3

Question MCQ▾

For the logic circuit shown in figure, the simplified Boolean expression for the output Y is,

Circuit Conducted NAND and nor Gates

Choices

Choice (4)Response

a.

B

b.

A

c.

A + B + C

d.

C

Edit

Question 4

Question MCQ▾

Which of the gate is not universal gates?

Choices

Choice (4)Response

a.

NAND gate

b.

NOR gate

c.

NAND & NOR gate

d.

AND & OR gate

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Question 5

Question MCQ▾

How to implement AND using NOR gate?

Choices

Choice (4)Response

a.

Circuit Conducted nor Gates Choice: A

b.

Circuit Conducted nor Gates Choice: B

c.

Question does not provide sufficient data or is vague

d.

All of the above

Edit

Question 6

Question MCQ▾

The simplified Boolean expression from karnaugh map is given in the figure is

K Map for Some Equation

Choices

Choice (4)Response

a.

b.

c.

d.

Edit

Question 7

Question MCQ▾

How to implement OR using NAND gate?

Choices

Choice (4)Response

a.

Circuit Conducted NAND Gates Choice: A

b.

Circuit Conducted NAND Gates Choice: B

c.

All of the above

d.

Question does not provide sufficient data or is vague

Edit