GATE Instrumentation: Questions 62 - 64 of 85

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Question number: 62

» Digital Electronics » IC Families, TTL, MOS and CMOS

Appeared in Year: 2014

MCQ▾

Question

The figure is a logic circuit with inputs A and B and output Y. Vss =+ 5 V. The circuit is of type

The circuit consisting two types of MOSFETs

The Circuit Consisting Two Types of MOSFETs

The circuit consisting two types of MOSFETs that are two of PMOS and two of NMOS

Choices

Choice (4) Response

a.

NAND

b.

AND

c.

NOR

d.

OR

Question number: 63

» Digital Electronics » Analog-to-Digital and Digital-to-Analog Converters

Appeared in Year: 2014

MCQ▾

Question

The circuit in the figure represents a counter-based unipolar ADC. When SOC is asserted the counter is reset and clock is enabled so that the counter counts up and the DAC output grows. When the DAC output exceeds the input sample value, the comparator switches from logic 0 to logic 1, disabling the clock and enabling the output buffer by asserting EOC. Assuming all components to be ideal, Equation , DAC output and input to be positive, the maximum error in conversion of the analog sample value is:

 R-2R ladder, control unit, comparator & UP counter

R-2R Ladder, Control Unit, Comparator & UP Counter

The circuit consisting R-2R ladder, control unit, comparator and UP counter

Choices

Choice (4) Response

a.

Directly proportional to clock frequency

b.

Inversely proportional to Equation

c.

Directly proportional to Equation

d.

Independent of Equation

Question number: 64

» Digital Electronics » IC Families, TTL, MOS and CMOS

Appeared in Year: 2014

MCQ▾

Question

A microprocessor accepts external interrupts (Ext INT) through a Programmable Interrupt Controller as shown in the figure.

The microprocessor with the programmable interrupt controller

The Microprocessor With the Programmable Interrupt Controller

The microprocessor with the programmable interrupt controller

Assuming vectored interrupt, a correct sequence of operations when a single external interrupt (Ext INT1) is received will be:

Choices

Choice (4) Response

a.

Ext INT1 → INT → INTA → Data Read

b.

Ext INT1 → INT → INTA → Address Write

c.

Ext INT1 → INT → Data Read → Address Write

d.

Ext INT1 → INTA → Data Read → INT

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