GATE Instrumentation: Questions 61 - 63 of 85

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Question number: 61

» Digital Electronics » Sequential Circuits,Flip-Flops, Counters, Shift Registers

Appeared in Year: 2012

MCQ▾

Question

Consider the given circuit

The combinational circuit consisting NAND gates

The Combinational Circuit Consisting NAND Gates

The combinational circuit consisting four NAND gates

In this circuit, the race around

Choices

Choice (4) Response

a.

Does not occur

b.

Occurs when CLK = 0

c.

Occurs when CLK = 1 and A = B = 1

d.

Occurs when CLK = 1 and A = B = 0

Question number: 62

» Digital Electronics » IC Families, TTL, MOS and CMOS

Appeared in Year: 2014

MCQ▾

Question

The figure is a logic circuit with inputs A and B and output Y. Vss =+ 5 V. The circuit is of type

The circuit consisting two types of MOSFETs

The Circuit Consisting Two Types of MOSFETs

The circuit consisting two types of MOSFETs that are two of PMOS and two of NMOS

Choices

Choice (4) Response

a.

NAND

b.

AND

c.

NOR

d.

OR

Question number: 63

» Digital Electronics » Analog-to-Digital and Digital-to-Analog Converters

Appeared in Year: 2014

MCQ▾

Question

The circuit in the figure represents a counter-based unipolar ADC. When SOC is asserted the counter is reset and clock is enabled so that the counter counts up and the DAC output grows. When the DAC output exceeds the input sample value, the comparator switches from logic 0 to logic 1, disabling the clock and enabling the output buffer by asserting EOC. Assuming all components to be ideal, Vref , DAC output and input to be positive, the maximum error in conversion of the analog sample value is:

 R-2R ladder, control unit, comparator & UP counter

R-2R Ladder, Control Unit, Comparator & UP Counter

The circuit consisting R-2R ladder, control unit, comparator and UP counter

Choices

Choice (4) Response

a.

Directly proportional to clock frequency

b.

Inversely proportional to Vref

c.

Directly proportional to Vref

d.

Independent of Vref

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