GATE (Graduate Aptitude Test in Engineering) Instrumentation: Questions 63 - 64 of 85

Access detailed explanations (illustrated with images and videos) to 85 questions. Access all new questions- tracking exam pattern and syllabus. View the complete topic-wise distribution of questions. Unlimited Access, Unlimited Time, on Unlimited Devices!

View Sample Explanation or View Features.

Rs. 100.00 -OR-

How to register? Already Subscribed?

Question 63

Appeared in Year: 2014

Question

MCQ▾

The circuit in the figure represents a counter-based unipolar ADC. When SOC is asserted the counter is reset and clock is enabled so that the counter counts up and the DAC output grows. When the DAC output exceeds the input sample value, the comparator switches from logic 0 to logic 1, disabling the clock and enabling the output buffer by asserting EOC. Assuming all components to be ideal, , DAC output and input to be positive, the maximum error in conversion of the analog sample value is:

R-2R Ladder, Control Unit, Comparator & up Counter

Choices

Choice (4)Response

a.

Directly proportional to clock frequency

b.

Directly proportional to

c.

Independent of

d.

Inversely proportional to

Question 64

Appeared in Year: 2014

Question

MCQ▾

A microprocessor accepts external interrupts (Ext INT) through a Programmable Interrupt Controller as shown in the figure.

The Microprocessor with the Programmable Interrupt Controller

Assuming vectored interrupt, a correct sequence of operations when a single external interrupt (Ext INT 1) is received will be:

Choices

Choice (4)Response

a.

Ext INT 1 ⇾ INTA ⇾ Data Read ⇾ INT

b.

Ext INT 1 ⇾ INT ⇾ INTA ⇾ Address Write

c.

Ext INT 1 ⇾ INT ⇾ Data Read ⇾ Address Write

d.

Ext INT 1 ⇾ INT ⇾ INTA ⇾ Data Read

Developed by: