Digital Circuits-Semiconductor Memories [GATE (Graduate Aptitude Test in Engineering) Electronics]: Questions 1 - 3 of 13

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Question 1

Appeared in Year: 1997

Question MCQ▾

Each cell of a static random access memory contains

Choices

Choice (4)Response

a.

1 MOS transistors and 1 capacitors

b.

6 MOS transistor

c.

2 MOS transistors and 4 capacitors

d.

4 MOS transistors and 2 capacitors

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Question 2

Appeared in Year: 2003

Question MCQ▾

In the circuit shown in the figure, A is parallel-in, parallel-out 4 bit register, which loads at the rising edge of the clock C. The input lines are connected to a 4 bit bus, W. Its output acts at input to a ROM whose output is floating when the input to a partial table of the contents of the ROM is as follows

The Table Contains Data and Address
Data00111111010010101011100000101000
Address02468101114

The clock to the register is shown, and the data on the W bus at time is 0110. The data on the bus at time is

A is Parallel-In, Parallel-Out 4 Bit Register with ROM

Choices

Choice (4)Response

a.

1000

b.

1011

c.

0010

d.

1111

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Question 3

Appeared in Year: 2001

Question MCQ▾

In the DRAM cell in the figure, the of the NMOSFET is 1 V. For the following three combinations of WL and BL voltages.

DRAM Cell with Three Combinations of WL and BL Voltages

Choices

Choice (4)Response

a.

5 V; 3 V; 7 V

b.

4 V; 3 V; 4 V

c.

5 V; 5 V; 5 V

d.

4 V; 4 V; 4 V

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