Digital Circuits [GATE (Graduate Aptitude Test in Engineering) Electronics]: Questions 229 - 232 of 271

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Question 229

Digital Circuits
Logic Gates and Their Static CMOS Implementation

Appeared in Year: 2014 (UGC-NET)

True-False▾

Statements

1. Gate is a combinational logic. (December)

2. JK Flip-flop in toggle mode is not combinational logic.

3. MSJK FF suffers from race-around.

4. Counters are sequential circuits.

Choices

Choice (4)Response

a.

None of the statements is correct.

b.

Both statement Ⅱ & statement Ⅲ are true.

c.

Statement Ⅱ, Ⅲ & Ⅳ are all true.

d.

Statement Ⅰ, Ⅱ & Ⅳ are all true.

Question 230

Digital Circuits
Boolean Algebra, Minimization of Functions

Appeared in Year: 2010

Question

MCQ▾

For the output F to be 1 in the logic circuit shown, the input combination should be

Choices

Choice (4)Response

a.

b.

c.

d.

Question 231

Digital Circuits
Logic Gates and Their Static CMOS Implementation

Appeared in Year: 2010

Question

Match List-Ⅰ List-Ⅱ▾

Match the logic gates in Column A with their equivalents in Column B.

List-Ⅰ (Column 1)List-Ⅱ (Column 2)
(A)
(i)
(B)
(ii)
(C)
(iii)
(D)
(iv)

Choices

Choice (4)Response
• (A)
• (B)
• (C)
• (D)

a.

• (ii)
• (iii)
• (iv)
• (i)

b.

• (iii)
• (ii)
• (iv)
• (i)

c.

• (i)
• (iv)
• (ii)
• (iii)

d.

• (ii)
• (i)
• (iv)
• (iii)

Question 232

Digital Circuits
Boolean Algebra, Minimization of Functions

Appeared in Year: 2016 (UGC-NET)

Question

MCQ▾

For the following circuit, for making the output high (1) , the input combination must be

Choices

Choice (4)Response

a.

and

b.

and

c.

and

d.

and

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