Digital Circuits [GATE (Graduate Aptitude Test in Engineering) Electronics]: Questions 158 - 161 of 271

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Question 158

Digital Circuits
Arithmetic Circuits, Code Converters, Multiplexers, Decoders and PLAs

Appeared in Year: 2016 (UGC-NET)

Question

MCQ▾

The logic function implemented by the circuit below is

Logic Function Implemented by the Circuit

Choices

Choice (4)Response

a.

Y =

b.

c.

Y = P. Q

d.

Question 159

Digital Circuits
Programming

Appeared in Year: 2018 (UGC-NET)

Question

MCQ▾

RAL is an example of (December)

Choices

Choice (4)Response

a.

Immediate Addressing mode

b.

Register Indirect Addressing mode

c.

Register addressing mode

d.

Implicit Addressing mode

Question 160

Digital Circuits
Architecture

Appeared in Year: 2018 (UGC-NET)

Question

MCQ▾

Two machine codes 3EH and 32H are stored in memory locations and 2001H respectively. The first machine code (3EH) represents the opcode to load a data byte in the accumulator, and the second code (32H) represents the data byte to be loaded in the accumulator. The time required executing the Opcode Fetch and the memory Read Cycles and the entire instruction cycle is, (if clock frequency is 2 MHz) . (December)

Choices

Choice (4)Response

a.

b.

c.

d.

Question 161

Digital Circuits
Shift-Registers and Finite State Machines

Appeared in Year: 2018 (UGC-NET)

Question

Assertion-Reason▾

Assertion(Ꭺ)

There are many applications in which digital outputs are required to be generated in accordance to the sequence in which input signals are received. (December)

Reason(Ꭱ)

These belong to such applications which only depend on the present input state.

Choices

Choice (4)Response

a.

Both Ꭺ and Ꭱ are true and Ꭱ is the correct explanation of Ꭺ

b.

Ꭺ is false but Ꭱ is true

c.

Both Ꭺ and Ꭱ are true but Ꭱ is NOT the correct explanation of Ꭺ

d.

Ꭺ is true but Ꭱ is false

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