Digital Circuits [GATE (Graduate Aptitude Test in Engineering) Electronics]: Questions 148 - 150 of 271

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Question 148

Digital Circuits
Architecture

Appeared in Year: 2018 (UGC-NET)

Question

MCQ▾

Arrange the following pins of in the descending order:

1) INTR

2)

3) MN/

4)

The correct sequence is: (July)

Choices

Choice (4)Response

a.

3) , 4) , 1) , 2)

b.

1) , 4) , 2) , 3)

c.

2) , 3) , 1) , 4)

d.

4) , 2) , 3) , 1)

Question 149

Digital Circuits
Arithmetic Circuits, Code Converters, Multiplexers, Decoders and PLAs

Question

MCQ▾

Suppose only one Multiplexer and one Inverter are allowed to be used to implement any Boolean functions of “n” variables. What is the maximum size of Multiplexer needed?

Choices

Choice (4)Response

a.

line to 1 line

b.

line to 1 line

c.

Line to 1 line

d.

line to 1 line

Question 150

Digital Circuits
Architecture

Appeared in Year: 2018 (UGC-NET)

Question

Assertion-Reason▾

Assertion(Ꭺ)

In microprocessor, the control buses and address buses are multiplexed. They can be demultiplexed by using ALE signals. (December)

Reason(Ꭱ)

The 8085 microprocessor signals can be classified in various groups, namely address bus, data bus, control bus and status signals, externally initiated signals and acknowledgement, power and frequency, serial I/O signals.

Choices

Choice (4)Response

a.

Both Ꭺ and Ꭱ are true and Ꭱ is the correct explanation of Ꭺ

b.

Both Ꭺ and Ꭱ are false

c.

Ꭺ is false but Ꭱ is true

d.

Ꭺ is true but Ꭱ is false

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