Digital Circuits [GATE (Graduate Aptitude Test in Engineering) Electronics]: Questions 80 - 83 of 271

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Question 80

Digital Circuits
Logic Gates and Their Static CMOS Implementation

Appeared in Year: 2009

Question

MCQ▾

The full form of the abbreviations TTL and CMOS in reference to logic families are

Choices

Choice (4)Response

a.

Triple Transistor Logic and Chip Metal Oxide Semiconductor

b.

Tristate Transistor Logic and Complementary Metal Oxide Silicon

c.

Tristate Transistor Logic and Chip Metal Oxide Semiconductor

d.

Transistor Transistor Logic and Complementary Metal Oxide Semiconductor

Question 81

Digital Circuits
Memory and I-O Interfacing

Appeared in Year: 2009

Question

MCQ▾

In a microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set, but the interrupt can be delayed or rejected Such an interrupt is

Choices

Choice (4)Response

a.

Non-maskable and non-vectored

b.

Maskable and vectored

c.

Maskable and non-vectored

d.

Non-maskable and vectored

Question 82

Digital Circuits
ROM, SRAM, DRAM

Appeared in Year: 1998

Question

MCQ▾

The noise margin of TTL gate is about

Choices

Choice (4)Response

a.

0.8 V

b.

0.2 V

c.

0.4 V

d.

0.6 V

Question 83

Digital Circuits
Shift-Registers and Finite State Machines

Appeared in Year: 2006

Question

MCQ▾

An I/O peripheral device shown in Figure below is to be interfaced to an 8085 microprocessor. To select the I/O device in the I/O address range D4H – D7 H, its chip-select () should be connected to the output of the decoder shown in as below:

The Input/Output Peripheral Device and 3 - 8 Decoder

Choices

Choice (4)Response

a.

Output 2

b.

Output 0

c.

Output 7

d.

Output 5

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