GATE (Graduate Aptitude Test in Engineering) Electronics: Questions 123 - 126 of 1076

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Question 123

Appeared in Year: 2006

Question

MCQ▾

Following is the segment of a 8085 assembly language program

  1. LXISP, EFFFH
  2. CALL3000H
  3. :
  4. :
  5. :
  6. 3000HLXIH, 3CF4
  7. PUSHPSW
  8. SPHL
  9. POPPSW
  10. RET

On completion of RET execution, the contents of SP is

Choices

Choice (4)Response

a.

EFFD H

b.

EFFF H

c.

3CF8 H

d.

3CF0 H

Question 124

Appeared in Year: 2001

Question

MCQ▾

A sequential circuit using D flip-flop and logic gates is shown in the figure, where X and Y are the inputs and Z is the inputs. The circuit is

The Sequential Circuit Using D-Flip-Flop and Logic Gates

Choices

Choice (4)Response

a.

S R - Flip-Flop with inputs X = R and Y = S

b.

S R - Flip-Flop with inputs X = S and Y = R

c.

J K - Flip-Flop with inputs X = J and Y = K

d.

J K - Flip-Flop with input X = K and Y = J

Question 125

Appeared in Year: 1998

Question

MCQ▾

For the TTL circuit shown in figure, find the current through the collector of transistor when

Assume and . The in its inverse active mode is 0.01.

TTL Circuit Having 4 Transistors

Choices

Choice (4)Response

a.

b.

c.

d.

Question 126

Appeared in Year: 2003

Question

MCQ▾

A 4 bit ripple counter and a bit synchronous counter are made using flip flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

Choices

Choice (4)Response

a.

R = 40 ns, S = 10 ns

b.

R = 10 ns, S = 40 ns

c.

R = 30 ns, S = 10 ns

d.

R = 10 ns S = 30 ns

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