GATE Electronics: Questions 93 - 95 of 271

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Question number: 93

» Digital Circuits » Number Systems; Combinatorial Circuits » Logic Gates and Their Static CMOS Implementation

Appeared in Year: 2002

MCQ▾

Question

The gates Equation and Equation in the figure have propagation delays of 10 ns and 20 ns respectively. If the input Equation , makes an output change from logic 0 to 1 at time Equation , then the output waveform Equation is,

The logic circuit given to find output wavelength

The Logic Circuit Given to Find Output Wavelength

The logic circuit having two gates EX-OR & NOR gate

Choices

Choice (4) Response

a.

The timing diagram of Choice A

The Timing Diagram of Choice A

Image showing the timing diagram

b.

The timing diagram of Choice B

The Timing Diagram of Choice B

Image showing the timing diagram

c.

The timing diagram of Choice C

The Timing Diagram of Choice C

Image showing the timing diagram

d.

The timing diagram of Choice D

The Timing Diagram of Choice D

Image showing the timing diagram

Question number: 94

» Digital Circuits » Semiconductor Memories » ROM, SRAM, DRAM

Appeared in Year: 2003

MCQ▾

Question

The output of the 74 series of GATE of TTL gates is taken from a BJT in

Choices

Choice (4) Response

a.

Either totem pole or open collector configuration

b.

Common base configuration

c.

Common collector configuration

d.

Totem pole and common collector configuration

Question number: 95

» Digital Circuits » Sequential Circuits » Latches and Flip-Flops

Appeared in Year: 2006

MCQ▾

Question

Two D flip-flops, as shown below, are to be connected as a synchronous counter that goes through the sequence Equation … The inputs D0 and D1 respectively should be connected as,

Choices

Choice (4) Response

a.

Equation And Equation

b.

Equation And Equation

c.

Equation And Equation

d.

Equation And Equation

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