GATE (Graduate Aptitude Test in Engineering) Electronics: Questions 97 - 101 of 1076

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Question 97

Logic Gates and Their Static CMOS Implementation

Appeared in Year: 1999

Question

MCQ▾

The minimized form of the logical expression, is,

Choices

Choice (4)Response

a.

b.

c.

d.

Question 98

Appeared in Year: 2011

Question

MCQ▾

Two D flip-flops are connected as a synchronous counter that goes through the following Q QB A sequence The connections to the inputs and are

Choices

Choice (4)Response

a.

b.

c.

d.

Question 99

Appeared in Year: 2010

Question

MCQ▾

In the circuit shown, the device connected Y5 can have address in the range

The Combinational Circuit Consisting 3 to 8 Decoder

Choices

Choice (4)Response

a.

FD00 - FDFF

b.

2E00 - 2EFF

c.

2000 - 20FF

d.

2D00 - 2DFF

Question 100

Boolean Algebra, Minimization of Functions

Appeared in Year: 2010

Question

MCQ▾

The Boolean function realized by the logic circuit shown is

The Combinational Circuit Consisting 4 to 1 Multiplexer

Choices

Choice (4)Response

a.

b.

c.

d.

Question 101

Appeared in Year: 2008

Question

MCQ▾

For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible Which of the following statements is true,

Logic Function Implemented by Various Types of Gates

Choices

Choice (4)Response

a.

Q goes to 0 at the CLK transition and stays 0

b.

Q goes to 1 at the CLK tradition and goes to 0 when D goes to 1

c.

Q goes to 0 at the CLK transition and goes to 1 when D goes to 1

d.

Q goes to 1 at the CLK transition and stays at 1

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