GATE (Graduate Aptitude Test in Engineering) Electronics: Questions 923 - 926 of 1076

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Question 923

Shift-Registers and Finite State Machines

Appeared in Year: 2019

Question

Numeric Answer▾

In the circuit shown, the clock frequency, i.e.. , the frequency of the Clk signal, is 12 kHz. The frequency of the signal at is ________ kHz. (Carry One Mark Each)

The Clock Frequency

Question 924

Diffusion Current, Drift Current, Mobility and Resistivity

Appeared in Year: 2016

Question

MCQ▾

A small percentage of impurity is added to an intrinsic semiconductor at . Which one of the following statements is true for the energy band diagram shown in the following figure?

The Energy Band Diagram Shown in the Following Figure

Choices

Choice (4)Response

a.

Intrinsic semiconductor doped with trivalent atoms to form type semiconductor.

b.

Intrinsic semiconductor doped with pentavalent atoms to form type semiconductor.

c.

Intrinsic semiconductor doped with trivalent atoms to form type semiconductor.

d.

Intrinsic semiconductor doped with pentavalent atoms to form type semiconductor.

Question 925

Logic Gates and Their Static CMOS Implementation

Appeared in Year: 2016

Question

Numeric Answer▾

The minimum number of input NAND gates required to implement a input XOR gate is …

Question 926

Appeared in Year: 2016

Question

MCQ▾

A closed-loop control system is stable if the Nyquist plot of the corresponding open-loop transfer function

Choices

Choice (4)Response

a.

Encircles the s-plane point in the clockwise direction as many times as the number of right-half s-plane poles.

b.

Encircles the s-plane point in the counter clockwise direction as many times as the number of right-half s-plane zeros.

c.

Encircles the s-plane point in the counter clockwise direction as many times as the number of left-half s-plane poles.

d.

Encircles the s-plane point in the counter clockwise direction as many times as the number of right-half s-plane poles.

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