GATE (Graduate Aptitude Test in Engineering) Electronics: Questions 50 - 53 of 1076

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Question 50

Appeared in Year: 1997

Question

MCQ▾

In a J-K flip-flop, we have and the given figure. Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the output will be,

J-K Flip-Flop with Its Output, Q¯is Given to the Input, J

Choices

Choice (4)Response

a.

010010

b.

011001

c.

010000

d.

010101

Question 51

Arithmetic Circuits, Code Converters, Multiplexers, Decoders and PLAs

Appeared in Year: 2001

Question

MCQ▾
A Combinational Circuit Using EX-Or, NAND, and Gates & LED

In the figure, the LED

Choices

Choice (4)Response

a.

Emits light when both S1 and S2 are closed

b.

Emits light when both S1 and S2 are open

c.

Does not emit light, irrespective of the switch positions.

d.

Emits light when only of S1 and S2 is closed

Question 52

Arithmetic Circuits, Code Converters, Multiplexers, Decoders and PLAs

Appeared in Year: 2008

Question

MCQ▾

For the circuit shown in the following, are inputs to the 4: 1 multiplexers, R (MSB) and S are control bits. The output X can be represented by

The Sequential Circuit Consists of 4 to 1 Multiplexer

Choices

Choice (4)Response

a.

b.

c.

d.

Question 53

Shift-Registers and Finite State Machines

Appeared in Year: 1997

Question

MCQ▾

Circuit shown in the figure is an NMOS shift register. All transistors are NMOS enhancement type with threshold voltage . Supply used is

Circuit Diagram with NMOS Shift Registers
The Clock Pulses for Clocks ϕ1 and ϕ2

All capacitors are initially discharged and input is applied. If values of the capacitors are find out voltage on capacitor after goes low.

Choices

Choice (4)Response

a.

1 V

b.

2.5 V

c.

1.5 V

d.

3.5 V

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